View CY7B992-7JC_6836724.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7b991 cy7b992 programmable skew clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07138 rev. *i revised march 21, 2011 programmable skew clock buffer features all output pair skew <100 ps typical (250 ps maximum) 3.75 mhz to 80 mhz output operation user selectable output functions ? selectable skew to 18 ns ? inverted and non-inverted ? operation at 1 2 and 1 4 input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz) zero input to output delay 50% duty cycle outputs outputs drive 50 terminated lines low operating current 32-pin plcc/lcc package jitter <200 ps peak-to-peak (< 25 ps rms) functional description the cy7b991 and cy7b992 programmable skew clock buffers (pscb) offer user selectable c ontrol over system clock functions. these multiple output clock driv ers provide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems. each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50 . they can deliver minimal and specified output skews and full swing logic levels (cy7b991 ttl or cy7b992 cmos). each output is hardwired to one of the nine delay or function configurations. delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs that skew up to 6 time units from their nominal ?zero? skew position. the completely integrated pll allows cancellation of external load and trans- mission line delay effects. when this ?zero delay? capability of the pscb is combined with the sele ctable output skew functions, you can create output-to-output delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions enable distribution of a low fre quency clock that are multiplied by two or four at the clock destinati on. this facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. test fb ref vco and time unit generator fs select inputs (three level) skew select matrix 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 filter phase freq det logic block diagram [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 2 of 21 contents pinouts .............................................................................. 3 block diagram description .............................................. 4 phase frequency detector and f ilter ............ .............. 4 vco and time unit generator ............. .............. ......... 4 skew select matrix ...................................................... 4 test mode .......................................................................... 5 maximum ratings ............................................................. 6 operating range ............................................................... 6 electrical characteristics ................................................. 7 capacitance ...................................................................... 8 switching characteristics .............................................. 11 ac timing diagrams ...................................................... 12 operational mode descriptions .................................... 13 ordering information ...................................................... 17 ordering code definitions . ....................................... 17 package diagrams .......................................................... 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 21 worldwide sales and design s upport ......... .............. 21 products .................................................................... 21 psoc solutions ......................................................... 21 [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 3 of 21 pinouts figure 1. pin configuration ? 32-pin plcc/lcc package table 1. pin definition signal name io description ref i reference frequency input. this input supplies the frequency and timing against which all functional variations are measured. fb i pll feedback input (typically connec ted to one of the eight outputs). fs i three level frequency range select. see ta b l e 2 . 1f0, 1f1 i three level function select inputs for output pair 1 (1q0, 1q1). see ta b l e 3 . 2f0, 2f1 i three level function select inputs for output pair 2 (2q0, 2q1). see ta b l e 3 . 3f0, 3f1 i three level function select inputs for output pair 3 (3q0, 3q1). see ta b l e 3 . 4f0, 4f1 i three level function select inputs for output pair 4 (4q0, 4q1). see ta b l e 3 . test i three level select. see ?test mode? on page 5 under the ?block diagram description? on page 4. 1q0, 1q1 o output pair 1. see ta b l e 3 . 2q0, 2q1 o output pair 2. see ta b l e 3 . 3q0, 3q1 o output pair 3. see ta b l e 3 . 4q0, 4q1 o output pair 4. see ta b l e 3 . v ccn pwr power supply for output drivers. v ccq pwr power supply for in ternal circuitry. gnd pwr ground. 1 2 3 4323130 17 16 15 14 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f0 fs v ref gnd test 2f1 fb 2q1 2q0 ccq 2f0 gnd 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3q1 3q0 ccn v ccn v 3f1 4f0 4f1 v ccq v ccn 4q1 4q0 gnd gnd cy7b991 cy7b992 [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 4 of 21 block diagram description phase frequency detector and filter the phase frequency detector and filter blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input and generate correction information to control the frequency of the voltage contro lled oscillator (vco). these blocks, along with the vco, form a phase locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block. it generates a frequency used by the time unit generator to create discrete time units that are selected in the skew select matrix. the operational range of the vco is determined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the le vel of the fs pin as shown in table 2 . skew select matrix the skew select matrix contains four independent sections. each section has two low skew, high fanout drivers (xq0, xq1), and two corresponding three level function select (xf0, xf1) inputs. ta b l e 3 shows the nine possible output functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. table 2. frequency range select and t u calculation [1] fs [2, 3] f nom (mhz) where n = approximate frequency (mhz) at which t u = 1.0 ns min max low 15 30 44 22.7 mid 25 50 26 38.5 high 40 80 16 62.5 t u 1 f nom n ----------------------- - = table 3. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1q1, 2q0, 2q1 3q0, 3q1 4q0, 4q1 low low ?4t u divide by 2 divide by 2 low mid ?3t u ?6t u ?6t u low high ?2t u ?4t u ?4t u mid low ?1t u ?2t u ?2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u divide by 4 inverted notes 1. for all tristate inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level is set on fs is determined by the ?normal? operating frequency (fnom) of the vco and time unit generator (see logic block diagram ). nominal frequency (fnom) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see ta b l e 3 ). the frequency appearing at the ref and fb inputs are fnom when the output connected to fb is undivided. t he frequency of the ref and fb inputs are fnom/2 or fnom/4 when the part is configured for a frequency multiplication by using a divided output as the fb input. 3. when the fs pin is selected high, the ref input must not transition upon power up until v cc has reached 4.3v. [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 5 of 21 test mode the test input is a three level input. in normal system operation, this pin is connected to ground, enabling the cy7b991 or cy7b992 to operate as explained in ?skew select matrix? on page 4 . for testing purposes, any of the three level inputs can have a removable jumper to ground, or be tied low through a 100 resistor. this enables an external tester to change the state of these pins. if the test input is forced to it s mid or high state, the device operates with its internal phas e locked loop disconnected, and input levels supplied to ref direct ly controls all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operation (test tied low), all outputs function based only on the connection of their own function selects inputs (xf0 and xf1) and the waveform characteristics of the ref input. figure 2 shows the typical outputs with fb connected to a zero skew output. [4] figure 2. typical outputs with fb connected to a zero-skew output t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fbinput refinput ? 6t u ? 4t u ? 3t u ? 2t u ? 1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert lm lh (n/a) ml (n/a) mm (n/a) mh (n/a) hl hm ll/hh hh 3fx 4fx (n/a) ll lm lh ml mm mh hl hm hh (n/a) (n/a) (n/a) 1fx 2fx note 4. fb connected to an output selected for ?zero? skew (i.e., xf1 = xf0 = mid). [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 6 of 21 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to +150 c ambient temperature with power applied .......................................... ?55 c to +125 c supply voltage to ground potentia l..............?0.5 v to +7.0 v dc input voltage ..........................................?0.5 v to +7.0 v output current into outputs (low)............................. 64 ma static discharge voltage........................................... >2001 v (mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5 v 10% industrial ?40 c to +85 c 5 v 10% [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 7 of 21 electrical characteristics over the operating range parameter description test conditions cy7b991 cy7b992 min max min max unit v oh output high voltage v cc = min i oh = ?16 ma 2.4 v v cc = min, i oh =?40 ma v cc ?0.75 v ol output low voltage v cc = min, i ol = 46 ma 0.45 v v cc = min, i ol = 46 ma 0.45 v ih input high voltage (ref and fb inputs only) 2.0 v cc v cc ? 1.35 v cc v v il input low voltage (ref and fb inputs only) ?0.5 0.8 ?0.5 1.35 v v ihh three level input high voltage (test, fs, xfn) [8] min v cc max v cc ? 0.85 v cc v cc ? 0.85 v cc v v imm three level input mid voltage (test, fs, xfn) [8] min v cc max v cc /2 ? 500 mv v cc /2 + 500 mv v cc /2 ? 500 mv v cc /2 + 500 mv v v ill three level input low voltage (test, fs, xfn) [8] min v cc maximum 0.0 0.85 0.0 0.85 v i ih input high leakage current (ref and fb inputs only) v cc = max, v in = max. 10 10 a i il input low leakage current (ref and fb inputs only) v cc = max, v in = 0.4 v ?500 ?500 a i ihh input high current (test, fs, xfn) v in = v cc 200 200 a i imm input mid current (test, fs, xfn) v in = v cc /2 ?50 50 ?50 50 a i ill input low current (test, fs, xfn) v in = gnd ?200 ?200 a i os output short circuit current [6] v cc = max, v out = gnd (25 c only) ?250 n/a ma i ccq operating current used by internal circuitry v ccn = v ccq = max, all input selects open com?l 85 85 ma ind 90 90 i ccn output buffer current per output pair [7] v ccn = v ccq = max, i out = 0 ma input selects open, f max 14 19 ma pd power dissipation per output pair [8] v ccn = v ccq = max, i out = 0 ma input selects open, f max 78 104 [9] mw notes 5. these inputs are normally wired to v cc , gnd, or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all datasheet limits are achieved. 6. cy7b991 must be tested one out put at a time, output shorted for less than one second, less than 10% duty cycle. room temperat ure only. cy7b992 outputs must not be shorted to gnd. doing so may cause permanent damage. 7. total output current per output pair is approximated by the following expression that includes device current plus load curre nt: cy7b991: i ccn = [(4 + 0.11f) + [((835 ? 3f)/z) + (.0022fc)]n] x 1.1 cy7b992: i ccn = [(3.5+ 0.17f) + [((1160 ? 2.8f)/z) + (.0025fc)]n] x 1.1 where f = frequency in mhz; c = capacitive load in pf; z = line impedance in ohms; n = number of loaded outputs; 0, 1, or 2; fc = f < c. 8. total power dissipation per output pair can be approximated by the following expression that in cludes device power dissipatio n plus power dissipation due to the load circuit: cy7b991:pd = [(22 + 0.61f) + [((1550 ? 2.7f)/z) + (.0125fc)]n] x 1.1 cy7b992:pd = [(19.25+ 0.94f) + [((700 + 6f)/z) + (.017fc)]n] x 1.1 see note 7 for variable definition. 9. applies to ref and fb inputs only. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 8 of 21 capacitance cmos output buffer current and power dissipa tion specified at 50 mhz reference frequency. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 10 pf figure 3. ac test loads and waveforms ttl ac test load (cy7b991) ttl input test waveform (cy7b991) 5v r1 r2 c l r1 r2 c l cmos ac test load (cy7b992) 3.0v 2.0v v th =1.5v 0.8v 0.0v 1ns 1ns 2.0v 0.8v v th =1.5v 80% v th =v cc /2 20% 0.0v 3ns 3ns 80% 20% v th =v cc /2 cmos input test waveform (cy7b992) v cc r1=130 r2=91 c l =50pf(c l =30 pf for ?2 and ?5 devices) (includes fixture and probe capacitance) r1=100 r2=100 c l =50pf(c l (includes fixture and probe capacitance) v cc =30 pf for ?2 and ?5 devices) [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 9 of 21 switching characteristics over the operating range [2, 11] cy7b991?2 [12] cy7b992?2 [12] parameter description min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2 , 3] 40 80 40 80 [13] t rpwh ref pulse width high 5.0 5.0 ns t rpwl ref pulse width low 5.0 5.0 ns t u programmable skew unit see ta b l e 2 t skewpr zero output matched-pair skew (xq0, xq1) [14, 15] 0.05 0.20 0.05 0.20 ns t skew0 zero output skew (all outputs) [14, 16,17] 0.1 0.25 0.1 0.25 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [14, 17] 0.25 0.5 0.25 0.5 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) [14, 17] 0.3 0.5 0.3 0.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [14, 17] 0.25 0.5 0.25 0.5 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [14, 17] 0.5 0.9 0.5 0.7 ns t dev device-to-device skew [12, 19] 0.75 0.75 ns t pd propagation delay, ref rise to fb rise ?0.25 0.0 +0.25 ?0.25 0.0 +0.25 ns t odcv output duty cycle variation [20] ?0.65 0.0 +0.65 ?0.5 0.0 +0.5 ns t pwh output high time deviation from 50% [21, 22] 2.0 3.0 ns t pwl output low time deviation from 50% [21, 22] 1.5 3.0 ns t orise output rise time [21, 23] 0.15 1.0 1.2 0.5 2.0 2.5 ns t ofall output fall time [21, 23] 0.15 1.0 1.2 0.5 2.0 2.5 ns t lock pll lock time [24] 0.5 0.5 ms t jr cycle-to-cycle output jitter rms [12] 25 25 ps peak-to-peak [12] 200 200 ps notes 10. cmos output buffer current and power dissipation specified at 50 mhz reference frequency. 11. test measurement levels for the cy7b991 are ttl levels (1.5 v to 1.5 v). test measurement levels for the cy7b992 are cmos le vels (v cc /2 to v cc /2). test conditions assume signal transition times of 2 ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 12. guaranteed by statistical correlation. tested initially and af ter any design or proc ess changes that affect these parameters . 13. except as noted, all cy7b992?2 and ?5 timing parame ters are specified to 80 mhz with a 30 pf load. 14. skew is defined as the time between the earliest and the late st output transition among all outputs for which the same tu de lay is selected when all are loaded with 50 pf and terminated with 50 to 2.06v (cy7b991) or v cc /2 (cy7b992). 15. tskewpr is defined as the skew between a pair of output s (xq0 and xq1) when all eight outputs are selected for 0tu. 16. tskew0 is defined as the skew between outputs when they are selected for 0tu. other outputs are divided or inverted but not shifted. 17. cl=0 pf. for cl=30 pf, tskew0=0.35 ns. 18. there are three classes of outputs: nominal (multiple of tu delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and d ivided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 19. tdev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, and so on.) 20. todcv is the deviation of the output from a 50% duty cycle. output pulse width variations are included in tskew2 and tskew4 specifications. 21. specified with outputs loaded with 30 pf for the cy7b99x?2 and ?5 devices and 50 pf for the cy7b99x?7 devices. devices are t erminated through 50 to 2.06v (cy7b991) or v cc /2 (cy7b992). 22. tpwh is measured at 2.0 v for the cy7b991 and 0.8 v cc for the cy7b992. tpwl is measured at 0.8v for the cy7b991 and 0.2 v cc for the cy7b992. 23. torise and tofall measured between 0.8v and 2.0v for the cy7b991 or 0.8 v cc and 0.2 v cc for the cy7b992. 24. tlock is the time that is required before synchronizati on is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until tpd is within specified limits. [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 10 of 21 switching characteristics over the operating range [2, 11] (continued) parameter description cy7b991?5 cy7b992?5 min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2 , 3] 40 80 40 80 [13] t rpwh ref pulse width high 5.0 5.0 ns t rpwl ref pulse width low 5.0 5.0 ns t u programmable skew unit see ta b l e 2 t skewpr zero output matched-pair skew (xq0, xq1) [14, 15] 0.1 0.25 0.1 0.25 ns t skew0 zero output skew (all outputs) [14, 16] 0.25 0.5 0.25 0.5 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [14, 17] 0.6 0.7 0.6 0.7 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) [14, 17] 0.5 1.0 0.6 1.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [14, 17] 0.5 0.7 0.5 0.7 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [14, 17] 0.5 1.0 0.6 1.7 ns t dev device-to-device skew [12, 19] 1.25 1.25 ns t pd propagation delay, ref rise to fb rise ?0.5 0.0 +0.5 ?0.5 0.0 +0.5 ns t odcv output duty cycle variation [20] ?1.0 0.0 +1.0 ?1.2 0.0 +1.2 ns t pwh output high time deviation from 50% [21, 22] 2.5 4.0 ns t pwl output low time deviation from 50% [21, 22] 3 4.0 ns t orise output rise time [21, 23] 0.15 1.0 1.5 0.5 2.0 3.5 ns t ofall output fall time [21, 23] 0.15 1.0 1.5 0.5 2.0 3.5 ns t lock pll lock time [24] 0.5 0.5 ms t jr cycle-to-cycle output jitter rms [12] 25 25 ps peak-to-peak [12] 200 200 ps [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 11 of 21 switching characteristics over the operating range [2, 11] (continued) cy7b991?7 cy7b992?7 parameter description min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2] 40 80 40 80 [13] t rpwh ref pulse width high 5.0 5.0 ns t rpwl ref pulse width low 5.0 5.0 ns t u programmable skew unit see table 2 t skewpr zero output matched-pair skew (xq0, xq1) [14, 15] 0.1 0.25 0.1 0.25 ns t skew0 zero output skew (all outputs) [14, 16] 0.3 0.75 0.3 0.75 ns t skew1 output skew (rise-ris e, fall-fall, same class outputs) [14, 17] 0.6 1.0 0.6 1.0 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) [14, 17] 1.0 1.5 1.0 1.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [14, 17] 0.7 1.2 0.7 1.2 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [14, 17] 1.2 1.7 1.2 1.7 ns t dev device-to-device skew [12, 20] 1.65 1.65 ns t pd propagation delay, ref rise to fb rise ?0.7 0.0 +0.7 ?0.7 0.0 +0.7 ns t odcv output duty cycle variation [20] ?1.2 0.0 +1.2 ?1.5 0.0 +1.5 ns t pwh output high time deviation from 50% [21, 22] 3 5.5 ns t pwl output low time deviation from 50% [21, 22] 3.5 5.5 ns t orise output rise time [21, 23] 0.15 1.5 2.5 0.5 3.0 5.0 ns t ofall output fall time [21, 23] 0.15 1.5 2.5 0.5 3.0 5.0 ns t lock pll lock time [24] 0.5 0.5 ms t jr cycle-to-cycle output jitter rms [12] 25 25 ps peak-to-peak [12] 200 200 ps [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 12 of 21 ac timing diagrams t odcv t odcv t ref ref fb q other q inverted q ref divided by 2 ref divided by 4 t rpwh t rpwl t pd t skewpr, t skew0, 1 t skewpr, t skew0, 1 t skew2 t skew2 t skew3, 4 t skew3, 4 t skew3, 4 t skew1,3, 4 t skew2, 4 t jr [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 13 of 21 operational m ode descriptions figure 4 shows the pscb configured as a zero skew clock buffer. in this mode the 7b991/992 is us ed as the basis for a low-skew clock distribution tree. when all of the func tion select inputs (xf0, xf1) are left open, the outputs are aligned and each driv es a terminated transmission line to an independent load. the fb input is tied to any output in this configuration and the operating frequency range is selected with the fs pin. the low-skew specification, coup led with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. figure 5 shows a configuration to equalize skew between metal traces of different lengths. in addition to low skew between outputs, the pscb is programmed to stagger the timing of its outputs. each of the four group s of output pairs are programmed to different output timing. skew timing is adjusted over a wide range in small increments with t he appropriate strapping of the function select pins. in this c onfiguration the 4q0 output is fed back to fb and configured for zero skew. the other three pairs of outputs are programmed to yield different skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. in this illustration the fb input is connected to an output with 0 ns skew (xf1, xf0 = mid) sele cted. the internal pll synchro- figure 4. zero skew and zero delay clock driver figure 5. programmable skew clock driver system clock l1 l2 l3 l4 length l1 = l2 = l3 = l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 length l1 = l2 l3 < l2 by 6 inches l4 > l2 by 6 inches system clock l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 14 of 21 nizes the fb and ref inputs and aligns their rising edges to ensure that all outputs have precise phase alignment. clock skews are advanced by 6 time units (tu) when using an output selected for zero skew as the feedback. a wider range of delays is possible if the output connected to fb is also skewed. since ?zero skew?, +tu, and ?t u are defined relative to output groups, and since the pll aligns the rising edges of ref and fb, you can create wider output skews by proper selection of the xfn inputs. for example, a +10 tu between ref and 3qx is achieved by connecting 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ?4 tu and 3qx skews to +6 tu, a total of +10 tu skew is realized.) many other configurations are realized by skewing both the outputs used as the fb input and skewing the other outputs. figure 6 shows an example of the invert function of the pscb. in this example the 4q0 output used as the fb input is programmed for invert (4f0 = 4f 1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this caus es the 1q, 2q, and 3q outputs to become the ?inverted? output s with respect to the ref input. it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outp uts by selecting the output connected to fb. the correct conf iguration is determined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4q. f figure 7 shows the pscb configured as a clock multiplier. the 3q0 output is programmed to divi de by four and is sent to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two, that results in a 40 mhz waveform at these outputs. no te that the 20 and 40 mhz clocks fall simul- taneously and are out of phase on their rising edge. this enables the designer to use the rising edges of the 1 2 frequency and 1 4 frequency outputs without concern for rising edge skew. the 2q0, 2q1, 1q0, and 1q1 output s run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80 mhz operatio n because that is the frequency of the fastest output. figure 8 demonstrates the pscb in a clock divider application. 2q0 is fed back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the falling edges of the 4qx and 3qx outputs are aligned. this enables the use of rising edges of the 1 2 frequency and 1 4 frequency without concern for skew mismatch. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15 mhz to 30 mhz figure 6. inverted output connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref figure 7. frequency multiplier with skew connections figure 8. frequency divider connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 20 mhz 40 mhz 80 mhz fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 5 mhz 10 mhz 20 mhz [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 15 of 21 range since the highest frequency output is running at 20 mhz. figure 9 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an inverted output enables the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. this function enables each of the two sub systems to clock 180 d egrees out of phase and align within the skew specifications. the divided outputs offer a zero delay divider for portions of the system that need the clock divided by either two or four, and still remain within a narrow skew of the ?1x? clock. without this feature, an external divider is added, and the propagation delay of the divider adds to the ske w between the different clock signals. these divided outputs, coupled with the phase locked loop, enables the pscb to multiply the clock rate at the ref input by either two or four. this mode enables the designer to distribute a low frequency clock between va rious portions of the system, and then locally multiply the clock rate to a more suitable frequency, still maintaining the low skew characteristics of the clock driver. the pscb performs all of the functions described in this section at the same time. it multiplies by two and four or divides by two (and four) at the same time. in other words, it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. figure 9. multi-function clock driver 20 mhz distribution clock 80 mhz inverted z 0 20 mhz 80 mhz zero skew 80 mhz skewed ?3.125 ns (?4t u ) fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref load load load load z 0 z 0 z 0 [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 16 of 21 figure 10 shows the cy7b991 and 992 connected in series to constr uct a zero skew clock distribution tree between boards. delays of the downstream clock buffers are programmed to compensate for the wire length (that is, sele ct negative skew equal to the wi re delay) necessary to connect them to the master clock source, approxima ting a zero delay clock tree. cascaded clock buffers accu mu- lates low frequency jitter because of the non-ideal filtering char acteristics of the pll filter. do not connect more than two c lock buffers in series. figure 10. board-to-board clock distribution system clock z 0 l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref fs fb load load load load load test z 0 z 0 z 0 [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 17 of 21 ordering code definitions ordering information accuracy (ps) ordering code package type operating range 500 cy7b991?5ji 32-pin plastic leaded chip carrier industrial cy7b991?5jit 32-pin plastic leaded chip carrier - tape and reel industrial 750 cy7b991?7ji 32-pin plastic leaded chip carrier industrial 750 cy7b992?7jc 32-pin plastic leaded chip carrier commercial cy7b992?7jct 32-pin plastic leaded chip carrier - tape and reel commercial cy7b992?7ji 32-pin plastic leaded chip carrier industrial pb-free 250 cy7b991?2jxc 32-pin plastic leaded chip carrier commercial cy7b991?2jxct 32-pin plastic leaded chip carrier - tape and reel commercial 500 cy7b991?5jxc 32-pin plastic leaded chip carrier commercial cy7b991?5jxct 32-pin plastic leaded chip carrier - tape and reel commercial cy7b991?5jxi 32-pin plastic leaded chip carrier industrial cy7b991?5jxit 32-pin plastic leaded chip carrier - tape and reel industrial 750 cy7b991?7jxc 32-pin plastic leaded chip carrier commercial cy7b991?7jxct 32-pin plastic leaded chip carrier - tape and reel commercial 500 cy7b992?5jxi 32-pin plastic leaded chip carrier industrial cy7b992?5jxit 32-pin plastic leaded chip carrier - tape and reel industrial 750 cy7b992?7jxc 32-pin plastic leaded chip carrier commercial cy7b992?7jxct 32-pin plastic leaded chip carrier - tape and reel commercial t = tape and reel, blank = tube temperature: c = comm ercial; i = industrial x = pb-free, blank = not pb-free j = plcc package speed grade: 2 / 5 / 7, based on propagation delay base part number 7b991 = clock buffer with ttl outputs 7b992 = clock buffer with cmos outputs company id: cy = cypress 7b99x cy (x) c (t) j x ? [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 18 of 21 package diagrams figure 11. 32-pin plastic leaded chip carrier 51-85002 *c [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 19 of 21 acronyms document conventions units of measure acronym description fb feedback pll phase-locked loop soic small-outline integrated circuit vco voltage controlled oscillator symbol unit of measure c degree celsius k kilohms mhz megahertz a microamperes ma milliamperes ms milliseconds mw milliwatts ns nanoseconds ohms % percent pf picofarads ppm parts per million ps picoseconds vvolts [+] feedback
cy7b991 cy7b992 document number: 38-07138 rev. *i page 20 of 21 document history page document title: cy7b991/cy7b992 pr ogrammable skew clock buffer document number: 38-07138 revision ecn orig. of change submission date description of change ** 110247 szv 12/19/01 change from specif ication number: 38-00513 to 38-07138 *a 1199925 kvm/aesa see ecn add pb-free part numbers. update package names in ordering information table. remove pentium reference on page 1. *b 1286064 aesa see ecn change status to final *c 2750166 tsai 08/10/09 post to external web *d 2761988 cxq 09/10/09 fixed ordering information ta ble replacement error of ?lead? with ?pb?. *e 2894960 kvm 03/18/10 removed following obsolete pa rts from the ordering information table: cy7b991-7lmb, cy7b992-7lmb, cy7b992-5ji, cy7b992-5jit updated package diagram updated sales links added table of contents *f 2905889 kvm 04/06/2010 removed inactive pa rt numbers cy7b991?2jc, cy7b991?2jct, cy7b991-5jc, cy7b991-5jct, cy7b991-7jc, cy7b991-7jct, cy7b992-2jc and cy7b992-2jct. *g 2950368 kvm 06/11/2010 added part numbers cy7b992-7jxc and cy7b992-7jxct removed remaining references to military specs. (all military devices were removed in a previous rev.) updated ordering information table *h 3045340 bash 10/07/2010 r emoved inactive part numbers cy7b992-5jc and cy7b992-5jct added ordering code definition *i 3201434 bash 03/21/2011 added acronyms and units tables. [+] feedback
document number: 38-07138 rev. *i revised march 21, 2011 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7b991 cy7b992 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY7B992-7JC

	To Download CY7B992-7JC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .